There is a continual goal in semiconductor wafer processing to maximize circuit density thereby minimizing the finished size of the semiconductor chip. One of the ways of minimizing the amount of surface area utilized for a given integrated circuit is to project the various devices and circuitry into the wafer, which is commonly known as vertical integration. As circuit complexity increases and vertical integration becomes more complex, the wafer topography becomes more and more varied. Differences in elevation might be as much as 50 to 100 percent or more across the die which can lead to severe problems in under-etching and over-etching of desired contacts. This gives rise to a need to etch contact/via openings of a given layer in multiple process steps because of a large variation in depth of the desired contacts at different points on the wafer.
The problem is diagrammatically illustrated by FIGS. 1 and 2. Referring to FIG. 1, a semiconductor wafer 10 includes a bulk substrate 12, field oxide regions 14, conductively doped silicon containing active regions 16a, 16b and 16c, and conductive runners 18a, 18b and 18c. The runners 18 are surrounded about their sides with spacer insulating material 20, which is typically oxide. A layer 22 of planarized dielectric oxide provides the top layer of the wafer. The goal or intent in the example is to etch contact openings to the upper surface of regions 16a, 16b and runner 18c. However, the elevation within dielectric layer 22 of the upper surface of runner 18c differs significantly from the elevation of the upper surfaces of regions 16a and 16b.
The problem during etch is illustrated by FIG. 2. Contact opening/vias 24a, 24b and 24c are illustrated as having been started within dielectric layer 22 over regions 16a, 16b and runner 18c, respectively. Opening 24c is illustrated as having been etched to the depth of the upper surface of runner 18c. However, further etching within dielectric layer 22 must occur for openings 24a and 24b to continue downwardly to the upper surfaces of regions 16a, 16b. During such continued etching, region 18c can be over etched, causing damage or destruction of runner 18c.
Typically, runner 18c will principally comprise silicon, such as conductively doped polysilicon, having an upper higher conductive silicide surface, such as WSi.sub.x or TiSi.sub.x. Insulating dielectric layer 22 will typically be principally composed of SiO.sub.2. Etch chemistries are preferably selected such that a greater amount of SiO.sub.2 is removed during the etch than is polysilicon at the point where the etch reaches contact 18c. Nevertheless, etch of exposed material of runner 18c while etch of openings 24a and 24b continues can be significant, resulting in damage or circuit failure.
One typical present way of overcoming this drawback is to conduct the photomasking and etch of openings 24a and 24b separately from the etch for opening 24c. Such multiple steps for contact etch reduce throughput time, and correspondingly increase costs of the overall process.
It is an object of this invention to overcome these and other drawbacks associated with the prior art.
The present invention is particularly pointed out and distinctly claimed at the end of this specification. However, the structures and methods of operation of one or more preferred embodiments may best be understood by reference to the following description taken in connection with the accompanying drawings wherein like reference characters refer to like elements.